1 rad-hard 16 channel bicmos analog multiplexer with high-z analog input protection hs-1840arh, hs-1840aeh, hs-1840brh, hs-1840beh the hs-1840arh, hs-1840aeh, hs-1840brh and hs-1840beh are radiation hardened, monolithic 16 channel multiplexers constructed with the intersil rad-hard silicon gate, bonded wafer, dielectric isolation process. they are designed to provide a high input impedance to the analog source if device powe r fails (open), or the analog signal voltage inadvertently exceeds the supply by up to 35v, regardless of whether the device is powered on or off. excellent for use in redundant applications, since the secondary devi ce can be operated in a standby unpowered mode affording no additional power drain. more significantly, a very high impedance exists between the active and inactive devices preventing any interaction. one of sixteen channel selections is controlled by a 4-bit bi nary address plus an enable-inhibit input which conveniently controls the on/off operation of several multiplexers in a system. all inputs have electrostatic discharge protection. the hs-1840arh, hs-1840aeh, hs-1840brh and hs-1840beh are processed and screened in full compliance with mil-prf-38535 and qml standards. the devices are available in a 28 ld sbdip and a 28 ld ceramic flatpack. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbers listed here must be used when ordering. detailed electrical specifications for these devices are contained in smd 5962-95630. a ?hot-link? is provided on our homepage for downloading: http://www.landandmaritime.dla.mil/downloads/milspec/smd/956 30.pdf features ? electrically screened to smd # 5962-95630 ? qml qualified per mil-prf-38535 requirements ? pin-to-pin for intersil?s hs-1840rh and hs-1840/883s ? improved radiation performance -gamma dose ( ) 3x10 5 rad(si) ?improved r ds(on) linearity ? improved access time 1.5s (max) over temp and post rad ? high analog input impedance 500m during power loss (open) ? 35v input overvoltage protection (power on or off) ? dielectrically isolated device islands ? excellent in hi-rel redundant systems ? break-before-make switching ?no latch-up caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2002, 2009-2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. april 6, 2012 fn4355.5
hs-1840arh, hs-1840aeh, hs-1840brh, hs-1840beh 2 fn4355.5 april 6, 2012 pin configurations ordering information ordering number internal mkt. number (note) temp. range (c) part marking no. package (rohs compliant) 5962f9563002qxc HS1-1840ARH-8 -55 to +125 q 5962f95 63002qxc 28 ld sbdip 5962f9563002qyc hs9-1840arh-8 -55 to +125 q 5962f95 63002qyc 28 ld flatpack 5962f9563002vxc HS1-1840ARH-q -55 to +125 q 5962f95 63002vxc 28 ld sbdip 5962f9563002vyc hs9-1840arh-q -55 to +125 q 5962f95 63002vyc 28 ld flatpack HS1-1840ARH/proto HS1-1840ARH/proto -55 to +125 hs1- 1840arh /proto 28 ld sbdip hs9-1840arh/proto hs9-1840arh/proto -55 to +125 hs9- 1840arh /proto 28 ld flatpack HS1-1840ARH-t HS1-1840ARH-t -55 to +125 q 5962r95 63002txc 28 ld sbdip 5962f9563002v9a hs0-1840arh-q -55 to +125 5962f9563004v9a hs0-1840aeh-q -55 to +125 5962f9563004vxc hs1-1840aeh-q -55 to +125 q 5962f95 63004vxc 28 ld sbdip 5962f9563004vyc hs9-1840aeh-q -55 to +125 q 5962f95 63004vyc 28 ld flatpack 5962f9563005v9a hs0-1840beh-q -55 to +125 5962f9563005vxc hs1-1840beh-q -55 to +125 q 5962f95 63005vxc 28 ld sbdip 5962f9563005vyc hs9-1840beh-q -55 to +125 q 5962f95 63005vyc 28 ld flatpack 5962f9563003qxc hs1-1840brh-8 -55 to +125 q 5962f95 63003qxc 28 ld sbdip 5962f9563003qyc hs9-1840brh-8 -55 to +125 q 5962f95 63003qyc 28 ld flatpack 5962f9563003vxc hs1-1840brh-q -55 to +125 q 5962f95 63003vxc 28 ld sbdip 5962f9563003vyc hs9-1840brh-q -55 to +125 q 5962f95 63003vyc 28 ld flatpack hs1-1840brh/proto hs1-1840brh/proto -55 to +125 hs1- 1840brh /proto 28 ld sbdip hs9-1840brh/proto hs9-1840brh/proto -55 to +125 hs9- 1840brh /proto 28 ld flatpack 5962f9563003v9a hs0-1840brh-q -55 to +125 note: these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant a nd compatible with both snpb and pb-free soldering operations. HS1-1840ARH, hs1-1840aeh, hs1-1840brh (28 ld sbdip) cdip2-t28 top view hs9-1840arh, hs9-1840aeh, hs9-1840brh (28 ld flatpack) cdfp3-f28 top view +v s nc nc in 16 in 15 in 14 in 13 in 12 in 11 in 10 in 9 gnd (+5v s ) v ref addr a3 out in 8 in 7 in 6 in 5 in 3 in 1 enable addr a0 addr a1 addr a2 -v s in 4 in 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +v s nc nc in 16 in 15 in 14 in 13 in 12 in 11 in 10 in 9 gnd (+5v s ) v ref addr a3 out -v s in 8 in 7 in 6 in 5 in 4 in 3 in 2 in 1 enable addr a0 addr a1 addr a2
hs-1840arh, hs-1840aeh, hs-1840brh, hs-1840beh 3 fn4355.5 april 6, 2012 functional diagram en digital address decoders address input buffer and level shifter multiplex switches a0 a1 a2 a3 1 16 v dd in1 out in16 note: mainswitch inxx: switch on, body tied to source switch off, body tied to vcc-0.7v mainswitch 16 mainswitch 1 table 1. truth table a3 a2 a1 a0 en ?on? channel xxxxh none lllll 1 lllhl 2 llhll 3 llhhl 4 lhlll 5 lhlhl 6 lhhll 7 lhhhl 8 hllll 9 hllhl 10 hlhll 11 hlhhl 12 hhl l l 13 hhlhl 14 hhhl l 15 hhhhl 16
hs-1840arh, hs-1840aeh, hs-1840brh, hs-1840beh 4 fn4355.5 april 6, 2012 burn-in/life test circuits figure 1. dynamic burn-in and life test circuit figure 2. .static burn-in test circuit notes: 1. the above test circuits are utilized for all package types. 2. the dynamic test circuit is utilized for all life testing. irradiation circuit hs-1840arh, hs-1840aeh, hs-1840brh note: 3. all irradiation testing is performed in the 28 lead cerdip package. r r gnd +v s r 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 f4 f3 f1 f5 f2 -v s note: v s + = +15.5v 0.5v, v s - = -15.5v 0.5v. r = 1k ? 5%. c 1 = c 2 = 0.01f 10%, 1 each per socket, minimum. d 1 = d 2 = 1n4002, 1 each per board, minimum. input signals: square wave, 50% duty cycle, 0v to 15v peak 10%. f1 = 100khz; f2 = f1/2; f3 = f1/4; f4 = f1/8; f5 = f1/16. 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 r r r gnd v r +v s r -v s note: r = 1k ? 5%, 1/4w. c 1 = c 2 = 0.01f minimum, 1 each per socket, minimum. v s + = 15.5v 0.5v, v s - = -15.5v 0.5v, v r = 15.5 0.5v 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1k +15v +1v +5v nc nc -15v 1 2 3 4 5 6 7 8 9 10 11 12 13 14
hs-1840arh, hs-1840aeh, hs-1840brh, hs-1840beh 5 fn4355.5 april 6, 2012 die characteristics die dimensions: (2820mx4080m x 483m 25.4 m) 111 milsx161 milsx19 mils 1 mil interface materials: glassivation: type: psg (phosphorus silicon glass) thickness: 8.0k ? 1k ? top metallization: ty pe : a l si c u thickness: 16.0k ? 2k ? backside finish: silicon assembly related information: substrate potential: unbiased (di) additional information: worst case current density: modified sem transistor count: 407 process: radiation hardened silicon gate, di wafer, dielectric isolation metallization mask layout hs-1840arh, hs-1840brh in7 in6 in5 in4 in3 in2 in1 enable a0 a1 a2 a3 v ref gnd in8 -v out +v in16 in15 in14 in13 in12 in11 in10 in9
hs-1840arh, hs-1840aeh, hs-1840brh, hs-1840beh 6 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn4355.5 april 6, 2012 for additional products, see www.intersil.com/product_tree ceramic dual-in-line me tal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d28.6 mil-std-1835 cdip2-t28 (d-10, configuration c) 28 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 1.490 - 37.85 - e 0.500 0.610 12.70 15.49 - e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n28 288 rev. 0 5/18/94
hs-1840arh, hs-1840aeh, hs-1840brh, hs-1840beh 7 fn4355.5 april 6, 2012 ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off- center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the finished lead surfac es, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from t he body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k28.a mil-std-1835 cdfp3-f28 (f-11a, configuration b) 28 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.740 - 18.80 3 e 0.460 0.520 11.68 13.21 - e1 - 0.550 - 13.97 3 e2 0.180 - 4.57 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.00 - 0.00 - 6 m - 0.0015 - 0.04 - n28 28- rev. 0 5/18/94
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